The problem arises when the output is high and the pull-up resistor is too large. If we look at the circuit, we observe that when the transistor is saturated, it presents a very low effective resistance to ground. One way to improve the rise time is to reduce the resistance value as is often done, but this also increases the power dissipation when the output is low. One of the problems with the TTL gate circuit is that the pull-up resistor on the output transistor will prevent rapid charging of any wiring capacitance on the output. A phase splitter transistor controls which transistor is active.The standard TTL output configuration with a HIGH output and a LOW output transistor, only one of which is active at any time.Connecting outputs causes excessively high currents to flow.Outputs must never be connected together.It is possible in TTL gates the charging of output capacitance without corresponding increase in power dissipation with the help of an output circuit arrangement referred to as an active pull-up or totem-pole output. At the same time, the collector of Q2 is sufficiently at LOW voltage level to keep Q3 OFF. As a result Q4 is turned ON by Q2, and producing LOW output which is near ground potential. This permits current through R1 and the base collector junction of Q1 into the base of Q2, thus driving Q2 into saturation. When A and B are high, the two input base emitter junctions of Q1 are reverse biased and its base collector junction is forward biased. At the same time, the emitter of Q2 is at ground potential, keeping Q4 OFF. Since Q3 acts as a emitter follower, by providing a low impedance path from Vcc to the output, making the output into HIGH. The collector of Q2 is HIGH and turns Q3 into saturation. Hence there is no current into the base of Q2 and making it into cur-off. Then there is a current from Vcc through R1 ti the base emitter junction of Q1 and into the LOW input, which provides a path to the ground for the current. If A or B is low, the base-emitter junction of Q1 is forward biased and its base-collector junction is reverse biased. the output transistors Q3 and Q4 form a totem-pole output arrangement. For the most part, we will consider the input transistor, act just like two diodes.Ī two input standard TTL NAND gate is a multiple emitter transistor for the inputs A and B. The analysis of this circuit follows very much the same path as the analysis of the DTL gate. Later on, we will make additional modifications to this circuit to improve its performance further. The input diodes are replaced by the multi-emitter NPN transistor. The p-n junction of diode is replaced by the BE junction of transistor and with the current gain of the transistor, the current going into the base of transistor is greatly increased, increasing the fanout. For example, the diode in the DTL can be replaced by a transistor whose collector is pulled up to the power supply. TTL is the most commonly used technology for SSI and MSI devices due to its low cost, high speed, and ready availability.The evolution from Diode transistor Logic to transistor transistor Logic can be seen by observing the placement of p-n junctions. It provides a good fan-out but cannot be connected to other TLL outputs as can open-collector outputs. The output stage has the property of providing a low-impedance drive for both positive and negative signals. The output stage, consisting of Q 3, D 1, Q 4, and R, acts as a power amplifier and is often termed a totem-pole output. Diode D 1 is included to establish the correct bias conditions for Q 4. The output thus increases to +5 volts, i.e. No current is available via Q 2 for Q 3's base, and so Q 3 turns off. If any one of the Q 1 inputs is returned to logic 0, 0 volts, then Q 1 is turned hard on, turning off Q 2 whose collector voltage rises this turns on Q 4.

The emitter voltage of Q 2 rises while its collector voltage falls, turning Q 3 on and Q 4 off. Thus if all inputs are at a high voltage (logic 1), all input “diodes” are reverse biased the collector voltage of Q 1 rises to V cc, turning on Q 2 (which acts as a phase splitter). Each base-emitter junction of Q 1 effectively acts as a diode, in a similar manner to a DTL input stage. The basic circuit uses a multiemitter bipolar transistor, Q 1, which is easily fabricated in integrated-circuit form. The diagram shows the equivalent circuit of a TTL two-input NAND gate. It is available in low power and high switching speed versions (see Schottky TTL), in addition to the standard form. A widely used family of logic circuits that is produced in integrated-circuit form and whose principal switching components are bipolar transistors.

Ttl transistor diagram and gate